Talk:Cyrix 6x86

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This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.

Models

Well spotted on the PR-133, 203.109.254.58. But I don't recall a PR-90. I'm not doubting that there was one, but my feeling is that it is better to ignore parts that were not marketed in more than tiny test quantities. The PR-90 certainly didn't figure in Cyrix's original public release plans, nor have I ever heard of one in the flesh. Was it actualy sold in commercial volumes? Or just a development part that maybe had a handful escape? Tannin

I read somewhere Cyrix had a 6x86 PR75 as well. I don't see any problem with listing rare parts.

This article says that the chip is 64bit. Is this in error? The Cyrix 6x86MX should be mentioned too, it went up to PR350.

PR

"It has six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+"

i'm sure i always saw theese advertised without the R and they were claimed to be pentium equvilence (e.g. p200+ was supposed to mean better than a 200mhz pentium iirc). Plugwash 02:22, 29 May 2006 (UTC)[reply]

Pipelining

The article says: "Unfortunately for the competition, Intel wanted to build a more powerful, more workstation-friendly CPU with the Pentium. They built by far their fastest FPU yet; a formidable pipelined unit, the first in an x86 CPU, that could also execute many important FPU instructions very quickly (low latency). Pipelining brought with it the ability to execute more than one instruction per clock cycle, giving it a decisive advantage over chips without a pipelined FPU. The poor FPU performance of the 6x86 can be mostly attributed to major FPU instructions taking at least 4 clocks, putting throughput at one quarter of the Intel P6's peak FPU execution rate. The FPU was not pipelined, and it also was no help that most programmers hand-tailored their code with optimizations designed for the Pentium's FPU. So, while the Pentium was speeding along executing various floating point instructions at a rate of more than one per clock cycle, the 6x86 was executing at a mere fraction of this rate. It was not much faster than a 486 FPU at the same clock speed."

I don't know much about the Pentium FPU, but I know that pipelining does not allow more than one instruction to be executed per clcok cycle - it allows several instructions to be executed simulataneously, but only one will be completed each cycle. I very much doubt the Pentium FPU could ever complete more than one instruction per clock cycle. Also, Pipelining was not a novel technique at this time - it was a major component of the RISC architectures of the mid-80s and the principle was understood in the 70s (see the MIPS architecture subject for refs).

At the end of the day though, I don't know what all this stuff about the pentium FPU architecture is doing here anyway. Wouldn't it be enough to say that the Pentium FPU was a lot faster, and programmers took advantage of this in a way Cyrix had not predicted? 194.30.171.59 10:59, 22 June 2006 (UTC)[reply]

This part should be removed

"It has been speculated by experts that 6x86 was designed to perform well specifically on business-oriented benchmarks of the time, most notably Ziff-Davis' Winstone benchmark."

What experts are they talking about? It seems as if a baseless claim was thrown in the article and they attempt to give it credibility by saying that "experts" said it. I had a Cyrix 6x86-PR166+, and it performed nicely. I think a more accurate statement would be that the 6x86 was designed to perform well specifically on business-oriented applications. TwinTurboZ 16:08, 24 March 2007 (UTC)[reply]

Regardless of these "experts," the real issue is the emphasis on integer performance in the CPU, which is certainly true and did make for superior "business" application performance of the chip.

However, when it was first introduced, the vast majority of all software (games, multimedia applications, business, etc) all had an emphasis on integer performance due to the dominance of 386 and 486 machines and the lack of FPU or relatively limited/slow FPUs used with those chips. (and since all those applications worked well -or at least reasonably well- with pure integer math -even 3D games focused on integer performance until the late 1990s) Quake was one of the first to push floating point performance . . . and the P5 Pentium played a major role in popularizing floating point usage in x86 PCs -since the FPU was actually faster than the ALU at some things, on top of floating point math being easier to use for 3D games. (integer math was still a workable alternative, but the emphasis on fast FPU performance on Intel, AMD and many RISC CPUs, combined with the greater ease of working with floating point math for 3D made for a shift towards that as the defacto-standard for mainstream game and some multimedia applications -certain game consoles, like the Playstation and Saturn, as well as embedded systems retained an emphasis on fixed-point math alone -including certain embedded/mobile devices to this day)

So, while the original 6x86 was not initially business-specific, by the time of the 68x6MX, the design was far more attractive for business (and other integer-specific) applications and less favorable for games and certain multimedia applications. (more so once 3DNow! and SSE arrived) — Preceding unsigned comment added by 207.62.201.22 (talk) 05:17, 8 February 2012 (UTC)[reply]

Named Techniques are not Risc(y)

"The 6x86 combines aspects of both RISC and CISC. It has a superscalar, superpipelined core, and performs register renaming, speculative execution, out-of-order execution, and data dependency removal.".

As far as I know the 6x86 is a CISC processor. It incorporates techniques to improve IPC but these techniques are neither typically CISC nor RISC. They can alos be incorporated into other types of instruction sets, VLIW for example. JVLebbink 07:40, 11 October 2007 (UTC)[reply]

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